1. Field of the Invention
The present invention relates to an output circuit for a semiconductor device.
2. Description of the Prior Art
As shown in FIG. 1, a conventional output circuit includes an interface 111, a voltage adjuster 121, a comparator 131, a controller 141, a counter 151, first through fifth data lines 121a-121e, and a latch unit 161. The interface 111 includes an external resister REXT having a termination voltage VTERM applied thereto. The voltage adjustor 121 includes first through fifth NMOS transistors Na through Ne connected in parallel between the interface 11 and the latch unit 161 via the first through fifth data lines 121a-121e. A drain and source of each of the first through fifth NMOS transistors Na through Ne are connected to the external resistor REXT and a ground voltage Vss, respectively. Also, an output voltage signal Vo is transmitted on a common connection between the external resistor REXT and the drains of the first through fifth NMOS transistors Na through Ne.
A positive input terminal (+) of the comparator 131 is connected to the common connection between the external resistor REXT of the interface 111 and the drains of the first through fifth NMOS transistors Na through Ne. A negative input terminal (-) of the comparator 131 receives a reference voltage VREF.
An input of the controller 141 is connected to the output of the comparator 131, and an input of the counter 151 is connected to the output of the controller 141. The counter 151 has first through fifth outputs connected to first through fifth data lines 121a through 121e, respectively. The first through fifth data lines 121a through 121e are connected to the gates of the first through fifth NMOS transistors Na through Ne, respectively, of the voltage adjustor 121. Also, the first through fifth data lines 121a through 121e are connected to first through fifth inputs of the latch unit 161, respectively. The latch unit 161 also has first through fifth outputs outputting a latched value.
Referring to FIG. 1, the operation of the conventional output circuit will now be described in detail.
During an initial operation, the controller 141 sends a control signal to the counter 151 to start an initial count operation. Then, the counter 151 outputs a zero value "00000" on the first through fifth data lines 121a through 121e. Thus, a value "0" signal is applied to the gates of the first through fifth NMOS transistors Na through Ne causing the first through fifth NMOS transistors Na through Ne to be turned "OFF". The relative resistances of the first through fifth NMOS transistors Na through Ne are 1X, 2X, 4X, 8X and 16X, respectively. The value "X" is a turn-on resistance value.
Because the first through fifth NMOS transistors Na through Ne are turned "OFF," no current flows from the external resistor REXT through any of the first through fifth NMOS transistors Na through Ne when a termination voltage VTERM is applied to the external resistor REXT. Thus, the termination voltage VTERM is outputted as the output voltage Vo on the common connection between the external resistor REXT and the drains of the first through fifth NMOS transistors Na through Ne.
For the initial operation, the voltage level relationship between the termination voltage VTERM, the reference voltage VREF, and the output voltage Vo is as follows: EQU VTERM&gt;VREF&gt;Vo
Therefore, the comparator 131 compares a voltage level of the termination voltage VTERM applied to its positive input terminal (+) with a voltage level of the reference voltage VREF applied to its negative input terminal (-). Since the voltage level of the termination voltage VTERM is larger than the voltage level of the reference voltage VREF, the comparator 131 outputs a positive value (+) to the controller 141. After receiving a positive value (+) from the comparator 131, the controller 141 sends a control signal to the counter 151 indicating the positive value (+). Based on the received control signal, indicating the positive value (+), the counter 151 initiates a count operation, and the count value increases by one (i.e., becomes 00001).
By outputting count value of 00001, the counter 151 outputs 00001 on the first through fifth data lines 121a through 121e, respectively. Thus, "1" on the first data line 121a is applied to the gate of the first NMOS transistor Na, and turns the first NMOS transistor Na "ON." Also, a "0" on the second through fifth data lines 121b through 121e is applied to the gates of the second through fifth NMOS transistors Nb through Ne, and turns the second through fifth NMOS transistors Nb through Ne "OFF."
As the first NMOS transistor Na is turned "ON," current flows through the external resistor REXT of the interface 111 and through the first NMOS transistor Na. This causes the output voltage Vo to change accordingly. Thus, the common connection between the external resistor REXT and the drains of the first through fifth NMOS transistors Na through Ne achieves a new output voltage Vo. The new output voltage Vo is applied to the positive input terminal(+) of the comparator 131. Then the voltage level of the new output voltage Vo is compared with the reference voltage VREF applied to the negative input terminal (-) of the comparator 131.
Based on the comparison result, if the output voltage Vo is still larger than the reference voltage VREF, the comparator 131 again outputs a positive value (+) to the controller 141. Then, the controller 141 outputs the control signal to the counter 151 indicating a positive value (+). The counter 151 counts to the next value of two (i.e., 00010) and outputs 00010 on the first through fifth data lines 121a through 121e, respectively.
Thus, the value of "1" on the second data line 121b is applied to the gate of the second NMOS transistor Nb; thereby turning the second NMOS transistor Nb "ON." In addition, the value of "0" on the first data line 121a and third through fifth data lines 121c through 121e is applied to the gates of the first NMOS transistor Na and the third through fifth NMOS transistors Nc through Ne; thereby turning the first NMOS transistor Na and the third through fifth NMOS transistors "OFF."
Therefore, current flows through the external resistor REXT of the interface 111 and through the second NMOS transistors Nb of the voltage adjustor 121. As a result, the output voltage Vo applied to the positive input terminal (+) of the comparator 131 changes accordingly.
While repeating the above procedure, if the output voltage level Vo becomes smaller than the voltage level of the reference voltage VREF, the comparator 131 will output a negative value (-) to the controller 141. Then, the controller 141 will send a control signal to the counter 151 to stop counting. Thus, the last count value on the first through fifth data lines 121a through 121e will be latched by the latch unit 161. The output of the latch unit 161 will then be used for determining the output voltage.
According to the conventional output circuit, a complicated circuit construction is required that includes the comparator, the counter, and the controller. Also, the conventional output circuit only operates after power is applied and stabilized to the output circuit and a reference voltage VREF is additionally required.